
  //
  // {{ tmpl.desc }}
  //
  axi_mem_wrapper #(
    .MEM_KB           ({{ tmpl.mem_size_kib }}),
    .ID_WIDTH         ({{ tmpl.txn_id_w }})
  ) u_{{ tmpl.name }} (
    .clk              ({{ tmpl.clk }}),
    .rst              ({{ tmpl.rst }}),
    .axi_mosi         (slaves_axi_mosi[{{ tmpl.slv_id }}]),
    .axi_miso         (slaves_axi_miso[{{ tmpl.slv_id }}])
  );

  // synthesis translate_off
  function automatic void writeWordRAM__{{ tmpl.name }}(addr_val, word_val);
    /*verilator public*/
    logic [31:0] addr_val;
    logic [31:0] word_val;
    u_{{ tmpl.name }}.mem_loading[addr_val] = word_val;
  endfunction
  // synthesis translate_on

